1. Field
Embodiments of the invention generally relate to an electrostatic chuck having reduced power loss, and methods and apparatus for reducing power loss in an electrostatic chuck, as well as methods for testing and manufacture thereof.
2. Description of the Related Art
In the manufacture of electronic devices on substrates, such as semiconductors and displays, many vacuum processes are utilized, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, implant, oxidation, nitridation, or other processes, to form the electronic devices. The substrates are typically processed one by one on an electrostatic chuck in a substrate processing chamber. To increase throughput, modern manufacturers often utilize a plurality of these substrate processing chambers operating in parallel (i.e., running a common process recipe). Each of the processing chambers may be the same make and model and are typically configured to process a substrate according to the common recipe. Thus, plural substrates may be processed within the same time period to produce identical product.
While the processing chambers may be substantially identical, subtle variations may exist between the processing chambers. The variations may require adjustment of the process parameters on one or more of the processing chambers to obtain “chamber match” or “chamber matching.” One methodology to reduce chamber on-wafer results in processing chambers utilizing radio frequency (RF) induced plasma processes modifies the RF power parameters of a particular processing chamber to compensate for a chamber-to-chamber variation in order produce a product that is in tolerance with other products that are processed in other processing chambers according to the common recipe. However, to modify the RF power parameters to obtain chamber matching, additional hardware is typically required. The additional hardware is often costly and typically does not address the root cause of the chamber-to-chamber variation.
Accordingly, it is desirable to reduce the chamber-to-chamber variations in on-wafer results in order to streamline parallel processing of substrates.